|
|
Post by karandeep963 on May 14, 2013 17:14:08 GMT
Hello All,
I was wondering if I can create a module with variable number of ports.
In other words, pass the number of ports as a parameter for the module constructor.
If not, how can I try to build my component?
If possible please relate with an example.
Regards,
KS
|
|
|
|
Post by anamikas on May 15, 2013 8:20:18 GMT
Hello All, I was wondering if I can create a module with variable number of ports. In other words, pass the number of ports as a parameter for the module constructor. If not, how can I try to build my component? If possible please relate with an example. Regards, KS There are two basic ways to do this 1. Use a constructor parameter 2. Use a template class The easiest to understand is the first. It's useful for parameterizing modules which need e.g. a different amount of dynamic memory when the module is declared. Another common use is to switch on debugging information. By using default values, it's possible to design the module so that some of the parameters may be left out if not needed. Here is a simple parameterized RAM model. The key is the use of a normal constructor together with the SC_HAS_PROCESS macro, instead of using SC_CTOR. #ifndef RAM_H #define RAM_H #include "systemc.h" SC_MODULE(ram) { sc_in<bool> clock; sc_in<bool> RnW; // ReadNotWrite sc_in<int> address; sc_inout<int> data; void ram_proc(); SC_HAS_PROCESS(ram); ram(sc_module_name name_, int size_=64, bool debug_ = false) : sc_module(name_), size(size_), debug(debug_) { SC_THREAD(ram_proc); sensitive << clock.pos(); buffer = new int ;
if (debug) {
cout << "Running constructor of " << name() << endl;
}
}
private:
int * buffer;
const int size;
const bool debug;
};
void ram::ram_proc()
{
while(true) {
wait(); // synchronous to rising edge
if (RnW) {
data = buffer[address];
}
else {
buffer[address] = data;
}
}
}
#endif
You'll have to write a testbench to test the ram fully. In the testbench, e.g. in sc_main, you can instance the ram:
ram r1("R1"); // 64 locations, debug off
ram r2("R2", 100); // 100 locations, debug off
ram r3("R3", 64, true); // 64 locations, debug on
|
|
|
|
Post by karandeep963 on May 15, 2013 9:24:40 GMT
Hello All, I was wondering if I can create a module with variable number of ports. In other words, pass the number of ports as a parameter for the module constructor. If not, how can I try to build my component? If possible please relate with an example. Regards, KS There are two basic ways to do this 1. Use a constructor parameter 2. Use a template class The easiest to understand is the first. It's useful for parameterizing modules which need e.g. a different amount of dynamic memory when the module is declared. Another common use is to switch on debugging information. By using default values, it's possible to design the module so that some of the parameters may be left out if not needed. Here is a simple parameterized RAM model. The key is the use of a normal constructor together with the SC_HAS_PROCESS macro, instead of using SC_CTOR. #ifndef RAM_H #define RAM_H #include "systemc.h" SC_MODULE(ram) { sc_in<bool> clock; sc_in<bool> RnW; // ReadNotWrite sc_in<int> address; sc_inout<int> data; void ram_proc(); SC_HAS_PROCESS(ram); ram(sc_module_name name_, int size_=64, bool debug_ = false) : sc_module(name_), size(size_), debug(debug_) { SC_THREAD(ram_proc); sensitive << clock.pos(); buffer = new int ;
if (debug) {
cout << "Running constructor of " << name() << endl;
}
}
private:
int * buffer;
const int size;
const bool debug;
};
void ram::ram_proc()
{
while(true) {
wait(); // synchronous to rising edge
if (RnW) {
data = buffer[address];
}
else {
buffer[address] = data;
}
}
}
#endif
You'll have to write a testbench to test the ram fully. In the testbench, e.g. in sc_main, you can instance the ram:
ram r1("R1"); // 64 locations, debug off
ram r2("R2", 100); // 100 locations, debug off
ram r3("R3", 64, true); // 64 locations, debug on
Could you please elaborate the concept , I was unable to understand from the above example that how the number of ports will be varied. Since what I understand from the above is the RAM paramterised for depth. I was wondering to create RAM which would be dual port or single port passed from the module constructor. Please enlighten the above concept. Thanks for replying Regards, KS |
|
|
|
Post by Akhil Kumar on May 17, 2013 10:35:26 GMT
Hello All, I was wondering if I can create a module with variable number of ports. In other words, pass the number of ports as a parameter for the module constructor. If not, how can I try to build my component? If possible please relate with an example. Regards, KS Can you please elaborate your question? |
|
|
|
Post by karandeep963 on May 20, 2013 5:03:02 GMT
Hello All, I was wondering if I can create a module with variable number of ports. In other words, pass the number of ports as a parameter for the module constructor. If not, how can I try to build my component? If possible please relate with an example. Regards, KS Can you please elaborate your question? Its the same I have requested above in reply to the first answer. Anyways I am re-writing it again
"I want to create RAM which would be dual port or single port passed from the module constructor".
Kindly ask if insufficient information. Regards, KS |
|
